Supply authentication via timing challenge response

ABSTRACT

In an example implementation, a print supply cartridge comprises a microcontroller to receive a timing challenge and enable authentication of the cartridge by providing a challenge response. The challenge response is provided in a challenge response time that falls within an expected time window.

BACKGROUND

Many systems have replaceable components that are integral to the functioning of the system. The replaceable components are often devices that contain consumable material that is depleted with each use of the system. Such systems may include, for example, cell phones that use replaceable batteries, medical systems that dispense medicine from replaceable supply devices, printing systems that dispense fluids (e.g., ink) or toilers from replaceable supply cartridges, and so on. Verifying that a replaceable supply device is an authentic device from a legitimate manufacturer can help a system user avoid problems associated with the unintended use of a defective and/or counterfeit device.

BRIEF DESCRIPTION OF THE DRAWINGS

The present embodiments will now be described, by way of example, with reference to the accompanying drawings, in which:

FIG. 1 shows a box diagram illustrating components of an example, generic authentication system suitable for authenticating a replaceable supply device;

FIG. 2 shows an example of characterization data stored on a replaceable supply device;

FIG. 3 shows an example of an authentication system embodied as an inkjet printing system;

FIG. 4 shows a perspective view of an example inkjet print supply cartridge;

FIG. 5 shows a flow diagram of an example supply authentication process.

Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements.

DETAILED DESCRIPTION

Overview

As noted above, verifying the authenticity of replaceable supply devices for use in certain systems can help system users avoid problems associated with the unintended use of defective and/or counterfeit devices. For example, in printing systems that employ consumable toner or ink cartridges, inadvertently replacing the cartridges with counterfeit cartridges can result in various problems ranging from poor quality printouts to leaky cartridges that can damage the printing system.

Prior methods of authenticating a replaceable device have included employing strong authentication that involves the use of a secret key known to a smart card or secure microcontroller on the replaceable device (e.g., consumable ink/toner cartridge) and the host device (e.g., printer). If the replaceable device can provide a response to a challenge issued by the host that proves t contains an appropriate key, the host will deduce that the device is of original manufacture, and then authenticate the device. One weakness with this method of authentication is that it relies on the ability of the system to preserve the secret key. If an attacker can recover a key or keys from either the host or the replaceable device, it can store the stolen key(s) in a smart card or microcontroller, enabling it to then create replaceable devices that will respond to challenges as if those devices were authentic devices from the original manufacturer. Typically, once the key(s) is compromised, the challenge response and other functionality of a non-authentic (i.e., counterfeit) replaceable device can be simulated with firmware running on an inexpensive, standard microcontroller.

Authentication systems and supply authentication processes are disclosed herein that provide for robust authentication of replaceable system devices, in general, through a timing challenge response. A host, such as a printer, issues a cryptographic timing challenge to a secure microcontroller affixed to a replaceable device, such as a consumable ink or toner cartridge. The challenge requests that the consumable device (i.e., the microcontroller on the consumable device) perform a number of mathematical operations based on data supplied by the host/printer. The printer monitors the amount of time it takes for the consumable device to complete the task, and independently verifies the response provided by the device. If the response and the time elapsed while computing the response both meet the expectations of the printer, the printer will conclude that the device is an authentic device. If either the response, or the time elapsed while computing the response (or both), does not meet the expectations of the printer, the printer will conclude that the device is not an authentic device.

The mathematical operations from the challenge are performed within the microcontroller of the consumable device by dedicated hardware logic specifically designed for such operations. The dedicated logic is capable of achieving the challenge response by performing the mathematical calculations significantly faster than could otherwise be achieved by a standard microcontroller executing firmware. Thus, a non-authentic/counterfeit replaceable device in which a microcontroller contains stolen key(s), may be capable of achieving a correct challenge response. However, such a counterfeit device is not capable of achieving the challenge response within a time frame expected by the host device.

In an example implementation, a print supply cartridge includes a microcontroller to receive a timing challenge and enable authentication of the cartridge by providing a challenge response in a challenge response time that falls within an expected time window. In another implementation, the cartridge further includes dedicated hardware logic on the microcontroller to perform a mathematical calculation in response to the timing challenge. Performing the mathematical calculation yields the challenge response within the expected time window.

In another example implementation, a replaceable supply device includes a microcontroller. The microcontroller is to derive a session key with a host device, and to receive a time-dependent challenge from the host device that specifies a random seed, the session key, and a calculation cycle. The replaceable device further includes dedicated logic within the microcontroller to perform a challenge calculation a number of times equal to the calculation cycle, wherein a first calculation uses the random seed and session key to produce an output, and each subsequent calculation uses an output of a preceding calculation.

In another example implementation, an authentication system includes a host device, a controller integrated into the host device, and an authentication algorithm executable on the controller to issue a cryptographic timing challenge and to authenticate the supply device when the supply device provides a challenge response in a challenge response time that falls within an expected time window.

In another example implementation, an authentication system includes a printer that has a controller and a memory. The authentication system also includes an authentication algorithm stored in the memory and executable on the controller to issue a cryptographic timing challenge and to authenticate a print supply cartridge when the cartridge provides a challenge response corresponding to an expected response within an expected time window.

In another example implementation, a non-transitory processor-readable medium stores code representing instructions that when executed by a processor cause the processor to recognize a supply device, and issue a cryptographic timing challenge to the supply device. The timing challenge requests a mathematical calculation to be performed on data that includes a session key, a random seed, and a calculation count. The instructions further cause the processor to receive a challenge response in a challenge response time from the supply device, and to authenticate the supply device when the challenge response matches an expected response and the challenge response time falls within an expected time window.

Example Implementations

FIG. 1 shows a box diagram illustrating components of an example, generic authentication system 100 suitable for authenticating a replaceable supply device. The authentication system 100 includes a host device 102 and a replaceable supply device 104. The host device 102 comprises a controller 106 that typically includes components of a standard computing system such as a processor (CPU) 108, a memory 110, firmware, and other electronics for controlling the general functions of the authentication system 100 and for communicating with and controlling supply device 104. Memory 110 can include both volatile (i.e., RAM) and nonvolatile (e.g., ROM, hard disk, floppy disk, CD-ROM, etc.) memory components comprising non-transitory computer/processor-readable media that provide for the storage of computer/processor-readable coded instructions and/or data in the form of algorithms, program modules, data structures, JDF, and so on. Supply device 104 comprises a microcontroller 112 (i.e., a smart card) that also includes a processor (CPU) 114 and a memory 116.

In general, upon power up of the host device 102, the host device 102 and supply device 104 establish secure communications through standard cryptographic techniques using standard cryptographic algorithms 118. For example, executing a cryptographic algorithm 118 (i.e., on processor 108), host device 102 can request the unique ID 120 of the supply device 104 and determine the device's “base key” 122 through a cryptographic relation. Using the base key 122, the host device and supply device can derive a secret “session key” 124 enabling secure communication for a current communication exchange. The host device 102 determines the base key 122 in this manner each time it is powered up, and each time a new supply device 104 is installed. The base key 122 remains the same and does not change. However, a new and different session key 124 is derived each time a communication exchange is made between the host device 102 and supply device 104.

In one implementation, memory 110 includes an authentication algorithm 126 executable on processor 108 of controller 106 to determine the authenticity of the replaceable supply device 104. The supply device 104 is determined to be authentic when it responds correctly to a cryptographic timing challenge 128 issued by the authentication algorithm 126, and when its response 130 to the challenge is completed within an expected window of time. Thus, a supply device 104 whose challenge response 130 value is correct, but whose challenge response time 131 does not fall within an expected window of time, is determined to not be authentic. Likewise, a supply device 104 whose challenge response time 131 falls within an expected window of time but whose challenge response 130 value is incorrect, is determined to not be authentic. The authenticity of the supply device 104, therefore, depends on it providing a correct response 130 to a cryptographic timing challenge 128 in a challenge response time 131 (i.e., the time it takes to provide the response 130) that falls within an expected window of time.

The cryptographic timing challenge 128 issued by the authentication algorithm 126 on host device 102 comprises a request to perform a specific mathematical calculation incorporating certain challenge parameters. The mathematical calculation is to be performed a particular number of times. The cryptographic timing challenge 128 includes or is accompanied by these challenge parameters, which include the derived session key, a random seed number generated on the host device 102 by controller 106, and a calculation count or cycle that indicates the number of times the calculation is to be performed. The mathematical calculation uses the session key and begins with an operation on the random seed number. The result or output of each calculation is repeatedly fed back into the next calculation until the calculation count has been reached. The last result or output of the mathematical calculation provides the challenge response 130, which will have been achieved or calculated in a particular challenge response time 131. The challenge response time 131 is measured by the authentication algorithm 126, for example, by starting a timing sequence when the challenge is issued, and stopping the timing sequence once the supply device 104 completes and returns the challenge response 130 to the host device 102. The challenge response time 131 is a temporary value that in some implementations may reside briefly on the host device 102 in a volatile component of memory 110 and/or within processor 108 prior to or during a comparison to a time window determined by the host. The authentication algorithm 126 on host 102 determines whether or not the challenge response 130 and the challenge response time 131 are correct (i.e., expected), and then authenticates the supply device 104 accordingly.

Referring still to FIG. 1, microcontroller 112 on supply device 104 comprises dedicated hardware challenge logic 132 for performing the mathematical calculation from a cryptographic timing challenge 128. The dedicated challenge logic 132 is specifically designed and fabricated on microcontroller 112 to optimally perform the particular mathematical calculation. In one example implementation, the mathematical calculation comprises a basic function that defines a sequence of operations optimized to run very fast in the dedicated logic 132. The mathematical calculation, or function, is iterated many times with the output of each iteration being part of the input to the next iteration. Thus, while one or more operands change with each iteration of the mathematical calculation, the mathematical calculation itself does not change. In addition, the challenge parameter values accompanying the timing challenge 128 may change with each timing challenge 128. Each timing challenge 128 issued by the authentication algorithm 126 to the supply device 104 may have different values for the session key, the random seed number generated on the host device 102 by controller 106, and the calculation count or cycle. Accordingly, for each timing challenge 128, the challenge response 130 and challenge response time 131 are determined by the challenge parameter values. More specifically, the session key, random seed, and calculation count all affect the challenge response value 130, while the calculation count also affects the challenge response time 131 by varying the number of iterations of the mathematical calculation through the dedicated challenge logic 132.

As noted above, the authentication algorithm 126 determines whether the challenge response 130 and the challenge response time 131, are correct or expected. This is done by comparing the challenge response 130 and response time 131 with correct or expected values. In different implementations, the algorithm 126 determines correct or expected values in different ways. In one implementation, for example, the algorithm 126 retrieves and accesses characterization data 134 stored on the supply device 104. The characterization data 134 can be secured with a digital signature and verified using standard cryptographic operations. The characterization data 134 provides expected time windows into which a challenge response time 131 should fall depending on the calculation count provided with the timing challenge 128. Thus, in one example as shown in FIG. 2, the characterization data 134 can include a table of data that associates different calculation count values with different time windows. By way of example only, such an association might indicate that for a calculation count of 10,000 (i.e., where the mathematical calculation is to be performed 10,000 times), the challenge response time 131 is expected to fall within a time window of 50-55 milliseconds. In another example, the characterization data 134 might be provided through a mathematical relation such as the slope-intercept formula, y=mx+b. Thus, for a given calculation count value, x, an expected time, y, can be determined. A time window can then be determined by the authentication algorithm 126 on host 102, for example, by using the expected time y, +/−5%.

In another example implementation, the authentication algorithm 126 determines correct or expected values for the challenge response 130 by issuing the cryptographic timing challenge 128 to dedicated reference logic 136 on the host device controller 106. The reference logic 136 on controller 106 mirrors the dedicated hardware logic 132 on the supply device 104, and is therefore specifically designed and fabricated on controller 106 to optimally perform the mathematical calculation from the timing challenge 128. Thus, when the authentication algorithm 126 issues the timing challenge 128 to the supply device 104, it also issues the timing challenge 128 to the reference logic 136. The reference logic 136 performs the mathematical calculations from the challenge in the same manner as discussed above with regard to the dedicated hardware logic 132 on the supply device 104. In response to the timing challenge 128, the reference logic 136 completes the challenge and provides a reference response in a reference time. A reference response time window can be defined, for example, to be within a certain percent (e.g., +/−5%, +/−10%) of the reference time. The authentication algorithm 126 can then use the reference response and the reference response time window as expected values to compare with the challenge response 130 and the challenge response time 131. If the challenge response 130 matches the reference response and the challenge response time 131 falls within the reference response time window, the algorithm 126 determines that the supply device 104 is an authentic device.

FIG. 3 shows an example of an authentication system 100 embodied as an inkjet printing system 300. In general, the printing system 300 comprises the same or similar components as the general authentication system 100, and functions in the same or similar manner regarding the authentication of replaceable inkjet supply cartridges. In an example implementation, the inkjet printing system 300 includes a print engine 302 having a controller 106, a mounting assembly 304, one or more replaceable supply devices 104 embodied as ink supply cartridges 306, and at least one power supply 308 that provides power to the various electrical components of inkjet printing system 300. Printing system 300 additionally includes media transport assembly 310.

FIG. 4 shows a perspective view of an example inkjet supply cartridge 306 that represents a replaceable supply device 104. In addition to one or more printheads 312, inkjet cartridge 306 includes a microcontroller 112, a group of electrical contacts 400, and an ink (or other fluid) supply chamber 402. In some implementations, cartridge 306 may have a supply chamber 402 that stores one color of ink, and in other implementations it may have a number of chambers 402 that each stores a different color of ink. Electrical contacts 400 carry electrical signals from controller 106 to nozzles 314 on printhead 312 to cause the ejection of fluid drops. Electrical contacts 400 also carry electrical signals between controller 106 and microcontroller 112 to facilitate the authentication of the cartridge 306 within the inkjet printing system 300. In one example implementation, microcontroller 112 is located on a silicon substrate shared by printhead 312. In another example implementation, microcontroller 112 is located elsewhere on the cartridge 306 as a stan-alone smart card. Microcontroller 112 is analogous to, and includes the same general components (not all shown in FIG. 4) of, the microcontroller 112 shown in FIG. 1 and discussed above. Thus, microcontroller 112 on cartridge 306 comprises memory 116 and dedicated challenge logic 132, which function in the same general manner as discussed above with regard to the authentication system 100 of FIGS. 1 and 2.

Referring to FIGS. 3 and 4, printhead 312 ejects drops of ink or other fluid through a plurality of orifices or nozzles 314 toward a print medium 316 so as to print onto print medium 316. Print media 316 can be any type of suitable sheet or roll material, such as paper, card stock, transparencies, Mylar, polyester, plywood, foam board, fabric, canvas, and the like. Printhead 312 can be configured to eject ink through nozzles 314 in a variety of ways. For example, a thermal inkjet printhead ejects drops from a nozzle by passing electrical current through a heating element to generate heat and vaporize a small portion of the ink within a firing chamber. The vapor bubble forces a drop of ink through the nozzle 314. In another example, a piezoelectric inkjet printhead uses a piezoelectric material actuator to generate pressure pulses that force ink drops out of a nozzle. Nozzles 314 are typically arranged in one or more columns or arrays along printhead 312 such that properly sequenced ejection of ink from nozzles 314 causes characters, symbols, and/or other graphics or images to be printed on print media 316 as inkjet cartridge 306 and print media 316 are moved relative to each other.

Mounting assembly 304 positions inkjet cartridge 306 relative to media transport assembly 310, and media transport assembly 310 positions print media 316 relative to inkjet cartridge 306. Thus, a print zone 318 is defined adjacent to nozzles 314 in an area between inkjet cartridge 306 and print media 316. In one implementation, print engine 302 is a scanning type print engine 302. As such, mounting assembly 304 includes a carriage for moving inkjet cartridge 306 relative to media transport assembly 310 to scan print media 316. In another implementation, print engine 302 is a non-scanning type print engine 302. As such, mounting assembly 304 fixes inkjet cartridge 306 at a prescribed position relative to media transport assembly 310 while media transport assembly 310 positions print media 316 relative to inkjet cartridge 306.

As noted above with regard to the authentication system 100 of FIG. 1, a controller 106 typically includes components of a standard computing system such as a processor (CPU) 108, a memory 110, firmware, and other electronics. In the inkjet printing system 300 of FIG. 3, controller 106 likewise employs such components for controlling the general functions of the printing system 300 and for communicating with and controlling inkjet cartridge 306, mounting assembly 304, and media transport assembly 310. Accordingly, controller 106 receives data 320 from a host system, such as a computer, and temporarily stores the data 320 in a memory 110. Typically, data 320 is sent to inkjet printing system 300 along an electronic, infrared, optical, or other information transfer path. Data 320 represents, for example, a document and/or file to be printed. As such, data 320 forms a print job for inkjet printing system 300 that includes one or more print job commands and/or command parameters. Using data 320, controller 106 controls inkjet cartridge 306 to eject ink drops from nozzles 314. Thus, controller 106 defines a pattern of ejected ink drops that form characters, symbols, and/or other graphics or images on print medium 316. The pattern of ejected ink drops is determined by the print job commands and/or command parameters from data 320.

In addition to managing the general printing functions of inkjet printing system 300, controller 106 executes an authentication algorithm 126 to determine whether an inkjet supply cartridge 306 is an authentic device. This authentication process on printing system 300 is similar to the process described above regarding the general authentication system 100 of FIG. 1. FIG. 5 is a flow diagram of an example authentication process 500 on a printing system 300 or other authentication system 100 that determines whether a replaceable supply device 104 such as an inkjet supply cartridge 306 is an authentic device. The process 500 is associated with the example implementations discussed above with regard to FIGS. 1-4, and details of the steps shown in process 500 can be found in the related discussion of such implementations. The steps of process 500 may be embodied as an algorithm comprising programming instructions stored on a non-transitory computer/processor-readable medium, such as memory 110 of FIGS. 1 and 3. In different examples, the implementation of the steps of process 500 is achieved by the reading and execution of such programming instructions by a processor, such as processor 108 of FIGS. 1 and 3. The process 500 may include more than one implementation, and different implementations of process 500 may not employ every step presented in the flow diagram of FIG. 5. Therefore, while steps of process 500 are presented in a particular order within the flow diagram, the order of their presentation is not intended to be a limitation as to the order in which the steps may actually be implemented, or as to whether all of the steps may be implemented. For example, one implementation of process 500 might be achieved through the performance of a number of initial steps, without performing one or more subsequent steps, while another implementation of process 500 might be achieved through the performance of all of the steps.

Referring now primarily to FIGS. 1, 3, and 5, an authentication process 500 begins at block 502, where the first step shown is to recognize a replaceable supply device. Recognizing a replaceable supply device typically occurs on power up of a host device or the insertion of a new supply device into a host device, such as when a printing system is turned on or when an ink or toner print supply cartridge is replaced in a printing system. The replaceable supply device can also be recognized when the supply device is powered up at the beginning of each print job. The authentication process 500 continues at block 504, where a cryptographic timing challenge is issued. The timing challenge is issued from a host device such as a printing device and sent to a supply device such as a print supply cartridge. The timing challenge comprises a request to perform a specific mathematical calculation involving certain challenge parameters that include a session key derived between a host device and a supply device, a random seed number generated by the host device, and a calculation count or cycle that indicates the number of times the calculation is to be performed. Upon issuing the timing challenge, the host device may begin a timing sequence to monitor the amount of time it takes to receive a challenge response, as shown at block 506.

In some implementations the timing challenge may also be sent to reference logic on the host device, as shown at block 508. When the timing challenge is sent to reference logic on the host device, a reference response is received from the logic in a certain amount of elapsed reference time, as shown at block 510. At block 512, a reference time window may be determined by including a range around the reference time of a certain percent. For example, a reference time window may be determined to be the reference time, plus or minus 5% of the reference time. In some implementations, as an alternative to sending the timing challenge to reference logic on the host device, the host device retrieves and accesses characterization data stored on the supply device, as shown at block 514. In another implementation, the characterization data may be hard-coded into a memory of the host device. The characterization data includes expected time windows for receiving a challenge response from the supply device that are associated with different calculation count values.

As shown at block 516, the authentication process 500 includes receiving a challenge response from the supply device. The challenge response is received in a certain challenge response time that can be determined, for example, by a time measurement on the host device. The process 500 continues at block 518 with comparing the challenge response to an expected response. The expected response can be the reference response received from the reference logic on the host device. At block 520, the challenge response time is also compared to an expected response time window to determine if the challenge response time falls within the expected time window. The expected time window can be the reference time window or an expected time window retrieved from the characterization data stored on the supply device or elsewhere.

The authentication process 500 continues at block 522 with the host device authenticating the supply device when the challenge response from the supply device matches an expected value and the challenge response time falls within an expected time window. At block 524 of process 500, the host device determines that the supply device is not authentic when either the challenge response does not match an expected value, or the challenge response time falls outside an expected time window, or both. 

What is claimed is:
 1. A device to facilitate authentication of a replaceable supply device, the device separate from a host, the device comprising: electrical contacts that communicate data with the host during operation; a Central Processing Unit (CPU); a memory including instructions that when executed by the CPU, cause the CPU to perform operations of: receiving a timing challenge from the host via the electrical contacts; and generating a plurality of session keys based on a base key, respective session keys specific to particular communications exchanges between the CPU and the host; the memory in communication with the CPU, the memory further including: a calculation count, the base key for authentication, and characterization data secured with a digital signature, the characterization data including a reference response time window, the memory incorporated into the device; and a hardware logic circuit, different from the CPU and the memory, the hardware logic circuit in communication with the CPU, and the hardware logic circuit to execute instructions to perform the operations of: performing an initial calculation based on a mathematical function with a random seed and one of the plurality of sessions keys as inputs; performing a number of additional calculations with the output of a prior calculation as input, the number of additional calculations based on the calculation count from the memory; and providing an output of a last of the additional calculations to the CPU; the instructions further cause the CPU to perform the operations of: determining an expected challenge response based on the output, the expected challenge response to be determined within the reference response time window based on structure of the logic circuit; and communicating the expected challenge response to the host via the electrical contacts within a challenge response time that falls within the reference response time window.
 2. The device of claim 1, wherein the challenge response time depends on the calculation count.
 3. The device of claim 1, the memory further having an identifier (ID).
 4. The device of claim 1, comprising a microcontroller that includes the CPU, the hardware logic circuit, and the memory.
 5. A replaceable supply cartridge comprising: a wall; a device disposed on or in the wall, the device including: electrical contacts that communicate data with a host during operation; a Central Processing Unit (CPU); a memory including instructions that when executed by the CPU, cause the CPU to perform operations of: receiving a timing challenge from the host via the electrical contacts; and generating a plurality of session keys based on a base key, respective session keys specific to particular communications exchanges between the CPU and the host; the memory in communication with the CPU, the memory further including characterization data secured with a digital signature, the characterization data including a calculation count and a reference response time window; and a hardware logic circuit, different from the CPU and the memory, the hardware logic circuit in communication with the CPU, and the hardware logic circuit to execute instructions to perform the operations of: performing an initial calculation based on a mathematical function with a random seed and one of the plurality of sessions keys as inputs; performing a number of additional calculations with the output of a prior calculation as input, the number of additional calculations based on the calculation count from the memory; and providing an output of a last of the additional calculations to the CPU; the instructions further cause the CPU to perform the operations of: determining an expected challenge response based on the output, the expected challenge response to be determined within the reference response time window based on structure of the logic circuit; and communicating the expected challenge response to the host via the electrical contacts within a challenge response time that falls within the reference response time window; and printing material in the replaceable supply cartridge, the printing material including at least one of an ink or a toner.
 6. A replaceable supply device comprising: a liquid supply chamber; and an authentication device to facilitate authentication of the replaceable supply device, the authentication device including: electrical contacts that communicate data with a host during operation; a Central Processing Unit (CPU); a memory including instructions that when executed by the CPU, cause the CPU to perform operations of: receiving a timing challenge from the host via the electrical contacts; and generating a plurality of session keys based on a base key, respective session keys specific to particular communications exchanges between the CPU and the host; the memory in communication with the CPU, the memory further including: the base key for authentication, and characterization data secured with a digital signature, the characterization data including a calculation count and a reference response time window; and a hardware logic circuit, different from the CPU and the memory, the hardware logic circuit in communication with the CPU, and the hardware logic circuit to execute instructions to perform the operations of: performing an initial calculation based on a mathematical function with a random seed and one of the plurality of sessions keys as inputs; performing a number of additional calculations with the output of a prior calculation as input, the number of additional calculations based on the calculation count from the memory; and providing an output of a last of the additional calculations to the CPU; the instructions further cause the CPU to perform the operations of: determining an expected challenge response based on the output, the expected challenge response to be determined within the reference response time window based on structure of the logic circuit; and communicating the expected challenge response to the host via the electrical contacts within a challenge response time that falls within the reference response time window.
 7. The device of claim 1, the characterization data including a listing of different reference response time windows in which to complete the challenge response, respective reference response time windows corresponding to different calculation counts.
 8. The device of claim 1, wherein the logic circuit is to execute instructions to perform the additional calculations including determining a reference response time window (y) based on a given calculation count (x) according to a slope-intercept formula (y=mx+b). 